1. Field of the Invention
The present invention relates generally to a method for forming a Shallow Trench Isolation (STI), and more particularly to a process for forming a Shallow Trench Isolation (STI) with etching the silicon nitride.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductor devices, become highly integrated the area occupied by the device shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. When the semiconductor device continuously shrinks to the deep sub-micron region, some problems described below are incurred due to the process of scaling down.
Shallow trench isolation (STI) is one of the isolation technologies applied to the fabrication of semiconductor devices. Cross-sectional views of a process for forming a salicide protected circuit of the known prior art are illustrated in FIG. 1A to FIG. 1D. First of all, a semiconductor substrate 100 is provided. Next, a pad oxide layer 110 is formed on the semiconductor substrate 100, and then a nitride layer 120 is formed on the pad oxide layer 110. Performing a photolithography process and an anisotropic etching process to form a trench 130 from the nitride layer 120 through the pad oxide 110 into the substrate 100. Afterward, a liner oxide 140 is deposited on surfaces of the nitride layer 120 and the trench 130 mentioned above. An oxide layer 150 serving as the isolation layer is subsequently deposited on the liner oxide 140 and polished by a Chemical Mechanical Polishing( CMP )process. The Chemical Mechanical Polishing (CMP) process removes the oxide layer 150 and the liner oxide 140 till the nitride layer 120 is exposed. Finally, removing the nitride layer 120, the liner oxide 140 and the isolation layer 150 until the surface of the pad oxide layer 110 on the semiconductor substrate 100.
The evolution of integrated circuits has evolved such that scaling down the device geometry is necessary. In the deep sub-micron technology of semiconductors, it""s necessary that the dimension of the device be decreased to reduce the space where the devices occupy. Therefore, a shallow trench isolation devices having a small size is formed by way of etching the nitride layer, so as to reduce the space that is occupied with the devices. Unfortunately, the conventional process for etching the nitride layer 120 will result in the corner-tipped 160 in the structure of the trench 130, so that the shallow trench isolation produces the high electric field and the pre-breakdown or the discharge-tipped effect when the dimension of the devices is scaled down, as shown in FIG. 1E.
Furthermore, if the structure of the shallow trench isolation is formed without the corner-tipped, a thermal process having a high temperature with a long processing time is performed after the conventional process for etching the nitride layer, so as to round off the corner-tipped. Therefore, the conventional process is very difficult to perform in below deep sub-micron. Especially, the method for forming the shallow trench isolation becomes more complex, a waste time, hence, an increase in cost.
In accordance with the above description, a new and improved method for forming the shallow trench isolation is therefore necessary, so as to raise the yield and quality of the follow-up process.
In accordance with the present invention, a method is provided for fabricating the shallow trench isolation that substantially overcomes the drawbacks of the above mentioned problems that arise from conventional methods.
Accordingly, it is a main object of the present invention to provide a method for fabricating the shallow trench isolation. This invention can use a residual etching process with a top rounding process to form the shallow trench isolation having better rounded corners. This will avoid the formation of the corner-tipped on the top of the trench structure that results in the high electric field and the pre-breakdown or the discharge-tipped effect when the dimension of the devices is scaled down. Hence, the present invention is appropriate for deep sub-micron technology in providing semiconductor devices.
Another object of the present invention is to provide a process for forming the shallow trench isolation. The present invention can from a convex remainder after etching the nitride layer by way of using a residual etching process, so as to round the top corner of the trench. Furthermore, this invention can use a thermal process having a low temperature with a short processing time to substitute for a thermal process having a high temperature long processing time during the follow-up process. Therefore, this invention can reduce the complexity of the conventional process and hence, endin cost reduction. Thus, the present invention can correspond to economic effect.
In accordance with the present invention, a new method for forming the semiconductor devices is disclosed. First of all, a semiconductor substrate that has a pad oxide layer thereon is provided. Then a dielectric layer is formed on the pad oxide layer. Afterward, a residual etching process is performed to etch the dielectric layer to form an opening and a convex remainder of the dielectric layer. The convex remainder of the dielectric layer and the semiconductor substrate are then etched by way of using a top rounding process to form the rounding corners on the semiconductor substrate. Subsequently, perform a process for forming the trench in order to form a trench with the rounding corners. Finally, the follow-up processes are performed to form the shallow trench isolation. Because the corners of the shallow trench isolation are rounded by way of using the residual etching process and the top rounding process, the high electric field and the pre-breakdown or the discharge-tipped effect are avoided. It is not necessary that the thermal process with high temperature is used to round the corners, whereby the process can be simplified and hence, cost down.